Semiconductor module with bond wire loop exposed from a molded body and method for fabricating the same

ABSTRACT

A semiconductor module includes a substrate, a semiconductor die arranged on the substrate, at least one first bond wire loop, wherein both ends of the at least one first bond wire loop are arranged on and coupled to a first electrode of the semiconductor die, and a molded body encapsulating the semiconductor die, wherein a top portion of the at least one first bond wire loop is exposed from a first side of the molded body.

TECHNICAL FIELD

This disclosure relates in general to semiconductor modules, inparticular to semiconductor modules wherein a bond wire loop is exposedfrom a molded body as well as to methods for fabricating the same.

BACKGROUND

Semiconductor module fabrication comprises various consecutive processsteps, e.g. attaching a die to a carrier, fabricating electricalinterconnects, encapsulation, etc. It may be desirable to perform anelectrical functionality test on semiconductor modules in fabricationprior to a particular step of the fabrication process. For example, thefabrication process may comprise a lamination step, wherein a laminateis arranged over a semiconductor die. It may be more cost efficient toperform the electrical functionality test prior to the lamination stepsince in the case the module has an electrical defect, the wholelaminated assembly would be a reject.

Furthermore, if the fabrication of the electrical interconnectscomprises a grinding process or a drilling process, there may be a riskthat the semiconductor die is damaged by the grinding or drillingequipment due to height tolerances.

Improved semiconductor modules and improved methods for fabricatingsemiconductor modules may help with solving these and other problems.The problem on which the invention is based is solved by the features ofthe independent claims. Further advantageous examples are described inthe dependent claims.

SUMMARY

Various aspects pertain to a semiconductor module comprising asubstrate, a semiconductor die arranged on the substrate, at least onefirst bond wire loop, wherein both ends of the first bond wire loop arearranged on and coupled to a first electrode of the semiconductor die,and a molded body encapsulating the semiconductor die, wherein a topportion of the at least one first bond wire loop is exposed from a firstside of the molded body.

Various aspects pertain to a method for fabricating a semiconductormodule, the method comprising: providing a substrate, arranging asemiconductor die on the substrate, fabricating at least one first bondwire loop on the semiconductor die such that both ends of the first bondwire loop are arranged on and coupled to a first electrode of thesemiconductor die, and encapsulating the semiconductor die in a moldedbody such that a top portion of the at least one first bond wire loop isexposed from a first side of the molded body.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate examples and together with thedescription serve to explain principles of the disclosure. Otherexamples and many of the intended advantages of the disclosure will bereadily appreciated in view of the following detailed description. Theelements of the drawings are not necessarily to scale relative to eachother. Identical reference numerals designate corresponding similarparts.

FIG. 1 shows a sectional view of a semiconductor module, wherein a bondwire loop is exposed from a molded body.

FIGS. 2A and 2B show a sectional view (FIG. 2A) and a perspective view(FIG. 2B) of a further semiconductor module, wherein a laminate isarranged over the molded body and the exposed bond wire loops. In FIG.2B the molded body, the laminate and the metallization are omitted.

FIGS. 3A and 3B each show an array of bond wire loops according to twodifferent examples.

FIGS. 4A to 4G show sectional views of a further semiconductor module invarious stages of fabrication, according to an exemplary method forfabricating semiconductor modules.

FIG. 5 shows a molding cavity configured for film assisted molding whichmay be used for fabricating a molded body from which a bond wire loop isexposed.

FIG. 6 is a flow chart of an exemplary method for fabricatingsemiconductor modules.

DETAILED DESCRIPTION

In the following detailed description, directional terminology, such as“top”, “bottom”, “left”, “right”, “upper”, “lower” etc., may be usedwith reference to the orientation of the Figure(s) being described.Because components of the disclosure can be positioned in a number ofdifferent orientations, the directional terminology is used for purposesof illustration only.

Furthermore, to the extent that the terms “include”, “have”, “with” orother variants thereof are used in either the detailed description orthe claims, such terms are intended to be inclusive in a manner similarto the term “comprise”. The terms “coupled” and “connected”, along withderivatives thereof may be used. It should be understood that theseterms may be used to indicate that two elements cooperate or interactwith each other regardless whether they are in direct physical orelectrical contact, or they are not in direct contact with each other;intervening elements or layers may be provided between the “bonded”,“attached”, or “connected” elements. However, it is also possible thatthe “bonded”, “attached”, or “connected” elements are in direct contactwith each other. Also, the term “exemplary” is merely meant as anexample, rather than the best or optimal.

The semiconductor modules described below may e.g. comprisesemiconductor dies comprising MOS transistor structures or verticaltransistor structures like, for example, IGBT (Insulated Gate BipolarTransistor) structures or, in general, transistor structures in which atleast one electrical contact pad is arranged on a first main face of thesemiconductor chip and at least one other electrical contact pad isarranged on a second main face of the semiconductor die, opposite to thefirst main face.

The semiconductor modules described below may include one or moresemiconductor dies. By way of example, one or more power semiconductorpower dies may be included. Further, one or more logic integratedcircuits may be included in the modules.

An efficient semiconductor module may for example reduce materialconsumption, ohmic losses, chemical waste etc. and may thus enableenergy and/or resource savings. Improved semiconductor modules andimproved methods for fabricating semiconductor modules, as specified inthis description, may thus at least indirectly contribute to greentechnology solutions, i.e. climate-friendly solutions providing amitigation of energy and/or resource use.

FIG. 1 shows a semiconductor module 100 which comprises a substrate 110,a semiconductor die 120, at least one first bond wire loop 130 and amolded body 140.

The semiconductor die 120 is arranged on the substrate 110, for examplesuch that a lower side (e.g. a backside) of the semiconductor die 120faces a first side 111 of the substrate 110. The at least one first bondwire loop 130 is configured such that both ends of the first bond wireloop 130 are arranged on and coupled to a first electrode 121 of thesemiconductor die 120. Furthermore, the molded body 140 encapsulates thesemiconductor die 120 such that a top portion 131 of the at least onefirst bond wire loop 130 is exposed from a first side 141 of the moldedbody 140.

The substrate 110 may be any suitable type of substrate, for example asubstrate of the type direct copper bond (DCB), direct aluminum bond(DAB), active metal brazing (AMB), insulated metal substrate (IMS),printed circuit board (PCB), leadframe, etc. Furthermore, the substrate110 may be a passive electric device, e.g. a capacitance, an inductor ora resistor, or it may be another semiconductor die.

The semiconductor die 120 may be any suitable type of semiconductor die,for example a power semiconductor die. The semiconductor module 100 maycomprise a single semiconductor die 120 or it may comprise severalsemiconductor dies 120. In the latter case, the semiconductor dies 120may be all identical or they may be different types of semiconductordies. According to an example, the semiconductor die 120 comprises anelectrode, e.g. a power electrode, on its lower side, wherein theelectrode is electrically coupled to the substrate 110. The electrode onthe lower side may for example be coupled to the substrate 110 by asolder joint.

The first electrode 121 may for example be a power electrode, e.g. asource, drain, emitter, or collector electrode, of the semiconductor die120. However, it may also be a control electrode like a gate electrodeor a sensing electrode. The first electrode 121 may comprise a layerstack of one or more metal layers or metal alloy layers. The at leastone first bond wire loop 130 may be coupled to an outermost layer of thelayer stack. The at least one first bond wire loop 130 may e.g. besoldered to the first electrode 121.

According to an example, layer stack of the first electrode 121comprises a Ti layer arranged on the semiconductor material of thesemiconductor die 120 and NiV layer arranged on the Ti layer. Anysuitable type of solder material, e.g. a solder comprising Sn, may beused to couple the first bond wire loop 130 to the first electrode 121.

According to an example, one end of the at least one first bond wireloop 130 is ball bonded to the first electrode 121 and the other end ofthe at least one first bond wire loop 130 is wedge bonded to the firstelectrode 121. According to another example, both ends of the at leastone first bond wire loop 130 are wedge bonded to the first electrode121. Using wedge bonds only may allow for the using thicker bond wiresto form the bond wire loops, e.g. bond wires with a diameter of 400 μm.Using ball bonds and wedge bonds may require using comparatively thinnerbond wires, e.g. bond wires with a diameter of 75 μm.

The semiconductor module 100 may comprise any suitable number of firstbond wire loops 130. All of the first bond wire loops 130 may be coupledto the first electrode 121 (in particular, both ends of each of thefirst bond wire loops 130 may be coupled to the first electrode 121).The first bond wire loops 130 may for example be arranged in an array onthe first electrode 121.

According to an example, the semiconductor module 100 may comprise oneor more further bond wire loops which may for example be coupled to oneor more further electrodes of the semiconductor die 120 or to thesubstrate 110 (in particular, both ends of a respective further bondwire loop may be coupled to a respective further electrode or to thesubstrate).

The first bond wire loop 130 may for example have a height measuredbetween the first electrode 121 and the top of the top portion 131 inthe range of 50 μm to 500 μm, in particular in the range of 100 μm to300 μm. The first bond wire loop 130 may for example have a spreadbetween the two ends of the first bond wire loop 130 measured in a planecomprising the first electrode 121 in the range of 300 μm to 3 mm, inparticular in the range of 500 μm to 1.5 mm. Adjacent first bond wireloops 130 may for example be spaced apart at a distance of 100 μm to 500μm, for example about 200 μm.

In the case that the semiconductor module 100 comprises more than onebond wire loop, the tops of all bond wire loops may essentially bearranged in the same plane above the first side 141 of the molded body140. The tops may e.g. be aligned in the same plane with an accuracy of+/−50 μm or better. In particular, the bond wire loops may help withcompensating for any fabrication tolerances of e.g. the height of thesubstrate 110 or tolerances in the height of a solder joint coupling thesemiconductor die 120 to the substrate 110.

The at least one first bond wire loop 130 may for example comprise abond wire with a thickness in the range of 75 μm to 400 μm. The bondwire may e.g. be a Cu wire. The at least one first bond wire loop 130may be configured to electrically connect the first electrode 121 to theoutside of the molded body 140. The at least one first bond wire loop130 may e.g. be configured to be operated at voltages of 750V or more,or 1200V or more.

The semiconductor module 100 may for example be configured to beoperable at temperatures of up to 175° C. for more than 1000 h and itmay be configured to be operable at temperatures of up to 200° C. for atleast several hours.

The molded body 140 may comprise any suitable dielectric mold material,in particular mold material with high temperature stability and/or gooddielectric properties. According to an example, the molded body 140 maycomprise filler particles, for example filler particles comprising orconsisting of silicon oxide or ceramics. The filler particles may beconfigured to improve the thermal and/or dielectric properties of themolded body 140. The filler particle content of the molded body 140 maye.g. be 70% or more and it may e.g. be as high as 95%. The fillerparticles may e.g. comprise or consist of silicon oxide or a ceramic.

The molded body 140 may essentially encapsulate the semiconductor die120 on all sides which do not face the substrate 110. The molded body140 may be solely arranged on the first side 111 of the substrate 110,as shown in FIG. 1. However, it is also possible that the molded body atleast partially covers further sides of the substrate 110. A thicknessof the molded body 140 above the upper side of the semiconductor die 120may for example be 50 μm or more, or 100 μm or more, or 200 μm or more,or 300 μm or more. The molded body 140 may for example be fabricatedusing a compression molding process or a transfer molding process.

FIGS. 2A and 2B show a further semiconductor module 200 which may besimilar to or identical with the semiconductor module 100, except forthe differences described in the following. FIG. 2A shows a sectionalview and FIG. 2B shows a perspective view.

The semiconductor module 200 comprises all components described withrespect to the semiconductor module 100 and it additionally comprises alaminate 150 and a metallization layer 160. The laminate 150 at leastpartially encapsulates the molded body 140. The metallization layer 160is arranged on a first side 151 of the laminate 150 and it is coupled tothe top portion 131 of the at least one first bond wire loop 130 by atleast one via 170 extending through the laminate 150. The metallizationlayer 160 may be a structured laver comprising contact pads andconductive tracks. In the perspective view of FIG. 2B the molded body140, the laminate 150, the metallization layer 160 and the vias 170 areomitted.

According to an example, the laminate 150 is part of a printed circuitboard configured for having one or more electronic components arrangedon and coupled to the metallization layer 160.

The laminate 150 may cover only the first side 141 of the molded body140, as shown in the example of FIG. 2. However, it is also possiblethat the laminate furthermore covers the lateral sides 142 of the moldedbody 140 and possibly also the lateral sides 112 of the substrate 110.Furthermore, the laminate 150 may also cover the second side 113 of thesubstrate 110.

The laminate 150 may for example comprise or consist of an epoxy resin.The laminate 150 may have a different material composition (a differentdielectric material and/or a different filler material) than the moldedbody 140. The laminate 150 may comprise filler material in the form of awoven fabric, whereas the filler particles of the molded body 140 mayessentially be individual spherical particles. A relative amount offiller material in the laminate 150 may be smaller, in particularconsiderably smaller, than a relative amount of filler particles in themolded body 140.

As shown in FIG. 2A, the laminate 150 may encapsulate the top portion131 of the at least one first bond wire loop 130 such that the topportion 131 is not exposed to the outside. The one or more vias 170 mayextend through the laminate 150 such that they contact the top portion131. The vias 170 may essentially be configured to bridge over theremaining distance between the top portion 131 and the metallizationlayer 170 in the laminate 150. The vias 170 in particular do not have toextend into the molded body 140 because the top portion 131 of the atleast one first bond wire loop is exposed from the molded body 140.

According to an example, the semiconductor module 200 further comprisesat least one second bond wire loop 180 which is arranged on and coupledto the substrate 110. In particular, both ends of the at least onesecond bond wire loop 180 may be coupled to the first side 111 of thesubstrate 110. Similar to the first bond wire loop 130, a top portion181 of the second bond wire loop 180 is exposed from the first side 141of the molded body 140.

The at least one second bond wire loop 180 may for example beelectrically coupled to an electrode on the lower side of thesemiconductor die 120 via the substrate 110. The at least one secondbond wire loop 180 may be coupled to the metallization layer 160 by oneor more of the vias 170.

The at least one second bond wire loop 180 may essentially be identicalto the at least one first bond wire loop 130, except that the at leastone second bond wire loop may have a greater height, because it has tobridge the thickness of the semiconductor die 120.

According to an example, e.g. in the case that the substrate is aleadframe, the substrate 110 may comprise several distinct parts, e.g. afirst substrate part 110_1 and a second substrate part 1102 (compareFIG. 2B). In this case, at least one second bond wire loop 180 may bearranged on a single one of the substrate parts 1101, 110_2 or at leastone second bond wire loop 180 may be arranged on each one of thesubstrate parts 110_1, 1102. The substrate parts 110_1, 110_2 may beelectrically coupled to each other by an electrical connector 190, e.g.a bond wire.

According to an example, the semiconductor module 100 or 200 comprisestwo semiconductor dies 120 and at least one third bond wire loop. The atleast one third bond wire loop may be identical to the first bond wireloop 130, except that its first end is coupled to an electrode on thefirst semiconductor die 120 and its second end is coupled to anelectrode on the second semiconductor die 120. In particular, the endsof the at least one third bond wire loop may be arranged on therespective electrode or the third bond wire loop may be indirectlyelectrically coupled to the respective electrode, e.g. via a substratepart.

FIGS. 3A and 3B show perspective views of an array of first bond wireloops 130 according to two different examples.

In the example shown in FIG. 3A, both ends of the first bond wire loops130 are wedge bonded to the semiconductor die 120. This also means thatconsecutive first bond wire loops 130 of a row of the array may be partof the same contiguous bond wire 310. In other words, each row of thearray may comprise a single contiguous bond wire 310.

In the example shown in FIG. 3B, one end of each first bond wire loop130 is wedge bonded and the other end is ball bonded to thesemiconductor die 120. In other words, each first bond wire loop 130comprises a distinct bond wire 310.

According to an example, the second bond wire loops 180 shown in FIG. 2may be configured similar to the array shown in FIG. 3A or similar tothe array shown in FIG. 3B.

With respect to FIGS. 4A to 4G a semiconductor module 400 is shown invarious stages of fabrication, according to an exemplary method forfabricating semiconductor modules. The semiconductor module 400 may besimilar to or identical with the semiconductor module 100 or 200.

As shown in FIG. 4A, the substrate 110 is provided. This may comprisearranging the substrate 110 on a temporary carrier 410, for example atape.

As shown in FIG. 4B, the semiconductor die 120 is arranged on thesubstrate 110. This may comprise soldering or gluing the lower side ofthe semiconductor die 120 to the first side 111 of the substrate 110.The semiconductor die 120 may or may not be electrically coupled to thesubstrate 110.

As shown in FIG. 4C, at least one first bond wire loop 130 is fabricatedon the semiconductor die 120 such that both ends of the first bond wireloop 130 are arranged on and coupled to the first electrode 121.Fabricating the bond wire loop(s) 130 may for example be done using aconventional wire bonding equipment. According to an example, an arrayof first bond wire loops 130 as e.g. shown in FIG. 3A or 3B is bonded tothe first electrode 121.

According to an example, at least one second bond wire loop 180 isfabricated on the substrate 110. The second bond wire loop(s) 180 may befabricated in the same bonding process as the first bond wire loop(s)130.

As shown in FIG. 4D, the semiconductor die 120 is encapsulated in themolded body 140 such that the top portion 131 of the at least one firstbond wire loop 130 is exposed from its first side 141.

According to an example, a transfer molding process or a compressionmolding process is used to fabricate the molded body 140. After themolding process, the top portion 131 of the first bond wire loop(s) 130may be covered by mold material, e.g. by a thin layer of mold material.A mold material removal process may be used to clean and expose the topportion(s) 131. This may e.g. comprise a chemical and/or mechanicaldeflashing of the top portion(s) 131 using e.g. a chemical softenerand/or a water jet.

The molded body 140 may be configured to prevent corrosion of ametallization of the semiconductor die 120, it may be configured to actas ion catcher for high voltage operation and it may have betterdielectric properties than a laminate does.

As shown in FIG. 4E, the laminate 150 is laminated over the molded body140 such that it covers the top portion 131 of the at least one firstbond wire loop 130. The lamination process may e.g. be performed afterthe molded body 130 has been cured.

Since the semiconductor die 120 is already encapsulated in the moldedbody 140, a risk that it is damaged by e.g. rough handling during thelamination process may be eliminated.

As shown in FIG. 4F, the top portion 131 of the at least one first bondwire loop 130 is exposed from the laminate 150 by drilling one or moreholes 420 into the laminate 150. The hole(s) 420 may for example bedrilled using a laser drilling process. The hole(s) 420 may e.g. bedrilled after the laminate 150 has been cured.

Since the hole(s) 420 need only extend to the top portion 131 of thefirst bond wire loop(s) 130 and not down to the first electrode 121,there is no risk that the first electrode 121 is accidentally damageddue to drilling the hole(s) 420 too deep. Furthermore, no grinding hasto be performed on the molded body 140 in order to fabricate anelectrical contact to the first electrode 121 because the first bondwire loop(s) 130 are exposed from the molded body 140.

As shown in FIG. 4G, the vias 170 are fabricated in the holes 420 andthe metallization layer 160 is fabricated on the first side 151 of thelaminate such that the metallization layer 160 is coupled to the topportion 131 of the at least one first bond wire loop 130 by the at leastone via 170.

FIG. 5 shows the substrate 110 with the semiconductor die 120 and the atleast one first bond wire loop 130 arranged in a molding cavity 500. Themolding cavity 500 may be used for fabricating the molded body 140.

As shown in FIG. 5, the molding cavity 500 may be equipped for filmassisted molding. In particular, the molding cavity 500 may beconfigured such that a film 510 covers the top portion 131 of the atleast one first bond wire loop 130 (and possibly also the top portion181 of the at least one second bond wire loop 180) and thereby preventit from being covered by liquid mold material.

According to another example, no film assisted molding process is used.In this case, an upper part 500_1 of the molding cavity 500 itself maybe configured to directly touch the top portions 131, 181 and completelyor partially prevent them from being covered by liquid mold material.The top portions 131, 181 may become covered by a thin layer of moldmaterial in this case, which can be removed by a deflashing process.

According to an example, the upper part 500_1 of the molding cavity 500is configured to press down onto the top parts 131, 180 of the bond wireloops 130, 180. This downward pressure may help with compensating forheight differences of individual bond wire loops due to fabricationtolerances and may ensure that all top portions 131, 181 are arrangedcoplanar with each other with a very high accuracy. Furthermore,pressing the bond wire loops 130, 180 into form like this may flattenthe top portions 131, 181 which may e.g. facilitate contacting them withthe vias 170. The flat top portions 131, 181 may be arranged in a planeparallel to the first side 141 of the molded body 140.

FIG. 6 is a flow chart of an exemplary method 600 for fabricating asemiconductor module. The method 600 may for example be used in thefabrication of the semiconductor modules 100, 200 and 400.

Method 600 comprises at 601 an act of providing a substrate, at 602 anact of arranging a semiconductor die on the substrate, at 603 an act offabricating at least one first bond wire loop on the semiconductor diesuch that both ends of the first bond wire loop are arranged on andcoupled to a first electrode of the semiconductor die, and at 604 an actof encapsulating the semiconductor die in a molded body such that a topportion of the at least one first bond wire loop is exposed from a firstside of the molded body.

In the following the semiconductor module as well as the method forfabricating a semiconductor module is further explained using specificexamples.

Example 1 is a semiconductor module, comprising: a substrate, asemiconductor die arranged on the substrate, at least one first bondwire loop, wherein both ends of the first bond wire loop are arranged onand coupled to a first electrode of the semiconductor die, and a moldedbody encapsulating the semiconductor die, wherein a top portion of theat least one first bond wire loop is exposed from a first side of themolded body.

Example 2 is the semiconductor module of example 1, wherein the at leastone first bond wire loop is part of an array of bond wire loops arrangedon and coupled to the first electrode.

Example 3 is the semiconductor module of example 1 or 2, furthercomprising: at least one second bond wire loop, wherein both ends of thesecond bond wire loop are arranged on and coupled to the substrate, andwherein a top portion of the at least one second bond wire loop isexposed from the first side of the molded body.

Example 4 is the semiconductor module of one of the preceding examples,wherein both ends of the at least one first bond wire loop are wedgebonded to the first electrode.

Example 5 is the semiconductor module of one of examples 1 to 3, whereinone end of the at least one first bond wire loop is ball bonded to thefirst electrode and the other end is wedge bonded to the firstelectrode.

Example 6 is the semiconductor module of one of the preceding examples,wherein the molded body comprises a content of filler particles of 70%or more.

Example 7 is the semiconductor module of one of the preceding examples,further comprising: a laminate at least partially encapsulating themolded body, and a metallization layer arranged on a first side of thelaminate and coupled to the top portion of the at least one first bondwire loop by at least one via extending through the laminate.

Example 8 is the semiconductor module of example 7, wherein the laminateis part of a printed circuit board configured for having one or moreelectronic components arranged on and coupled to the metallizationlayer.

Example 9 is the semiconductor module of one of the preceding examples,wherein the substrate is a leadframe, a direct copper bond, a directaluminum bond, an active metal brazing, a resistor, a capacitance, aninductor, or a further semiconductor die.

Example 10 is the semiconductor module of one of the preceding examples,wherein a loop height of the at least one first bond wire loop is 100 μmor more.

Example 11 is a method for fabricating a semiconductor module, themethod comprising: providing a substrate, arranging a semiconductor dieon the substrate, fabricating at least one first bond wire loop on thesemiconductor die such that both ends of the first bond wire loop arearranged on and coupled to a first electrode of the semiconductor die,and encapsulating the semiconductor die in a molded body such that a topportion of the at least one first bond wire loop is exposed from a firstside of the molded body.

Example 12 is the method of example 11, wherein the encapsulatingcomprises compression molding or transfer molding over the semiconductordie in a molding cavity, wherein the molding cavity is configured suchthat the top portion of the at least one first bond wire loop is notcovered by mold compound.

Example 13 is the method of example 12, wherein film assisted molding isused to prevent the top portion of the at least one first bond wire loopfrom being covered by mold compound.

Example 14 is the method of one of examples 11 to 13, furthercomprising: laminating over the molded body such that the laminatecovers the top portion of the at least one first bond wire loop,arranging a metallization layer on a first side of the laminate, andcoupling the metallization layer to the top portion of the at least onefirst bond wire loop by at least one via extending through the laminate.

Example 15 is the method of example 14, wherein the coupling comprisesexposing the top portion of the at least one first bond wire loop fromthe laminate by laser drilling and forming a via in the drilled hole.

Example 16 is an apparatus comprising means for performing the methodaccording to anyone of examples 11 to 15.

While the disclosure has been illustrated and described with respect toone or more implementations, alterations and/or modifications may bemade to the illustrated examples without departing from the spirit andscope of the appended claims. In particular regard to the variousfunctions performed by the above described components or structures(assemblies, devices, circuits, systems, etc.), the terms (including areference to a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component or structurewhich performs the specified function of the described component (e.g.,that is functionally equivalent), even though not structurallyequivalent to the disclosed structure which performs the function in theherein illustrated exemplary implementations of the disclosure.

What is claimed is:
 1. A semiconductor module, comprising: a substrate;a semiconductor die arranged on the substrate; at least one first bondwire loop, wherein both ends of the at least one first bond wire loopare arranged on and coupled to a first electrode of the semiconductordie; and a molded body encapsulating the semiconductor die, wherein atop portion of the at least one first bond wire loop is exposed from afirst side of the molded body.
 2. The semiconductor module of claim 1,wherein the at least one first bond wire loop is part of an array ofbond wire loops arranged on and coupled to the first electrode.
 3. Thesemiconductor module of claim 1, further comprising: at least one secondbond wire loop, wherein both ends of the at least one second bond wireloop are arranged on and coupled to the substrate, wherein a top portionof the at least one second bond wire loop is exposed from the first sideof the molded body.
 4. The semiconductor module of claim 1, wherein bothends of the at least one first bond wire loop are wedge bonded to thefirst electrode.
 5. The semiconductor module of claim 1, wherein one endof the at least one first bond wire loop is ball bonded to the firstelectrode and the other end is wedge bonded to the first electrode. 6.The semiconductor module of claim 1, wherein the molded body comprises acontent of filler particles of 70% or more.
 7. The semiconductor moduleof claim 1, further comprising: a laminate at least partiallyencapsulating the molded body; and a metallization layer arranged on afirst side of the laminate and coupled to the top portion of the atleast one first bond wire loop by at least one via extending through thelaminate.
 8. The semiconductor module of claim 7, wherein the laminateis part of a printed circuit board configured for having one or moreelectronic components arranged on and coupled to the metallizationlayer.
 9. The semiconductor module of claim 1, wherein the substrate isa leadframe, a direct copper bond, a direct aluminum bond, an activemetal brazing, a resistor, a capacitance, an inductor, or a furthersemiconductor die.
 10. The semiconductor module of claim 1, wherein aloop height of the at least one first bond wire loop is 100 μm or more.11. A method for fabricating a semiconductor module, the methodcomprising: providing a substrate; arranging a semiconductor die on thesubstrate; fabricating at least one first bond wire loop on thesemiconductor die such that both ends of the at least one first bondwire loop are arranged on and coupled to a first electrode of thesemiconductor die; and encapsulating the semiconductor die in a moldedbody such that a top portion of the at least one first bond wire loop isexposed from a first side of the molded body.
 12. The method of claim11, wherein the encapsulating comprises compression molding or transfermolding over the semiconductor die in a molding cavity, wherein themolding cavity is configured such that the top portion of the at leastone first bond wire loop is not covered by mold compound.
 13. The methodof claim 12, wherein film assisted molding is used to prevent the topportion of the at least one first bond wire loop from being covered bymold compound.
 14. The method of claim 11, further comprising:laminating over the molded body such that the laminate covers the topportion of the at least one first bond wire loop; arranging ametallization layer on a first side of the laminate; and coupling themetallization layer to the top portion of the at least one first bondwire loop by at least one via extending through the laminate.
 15. Themethod of claim 14, wherein the coupling comprises: exposing the topportion of the at least one first bond wire loop from the laminate by adrilled hole formed by laser drilling; and forming a via in the drilledhole.